Circuit miniaturization and system miniaturization are well known goals in the electronics industry. Much miniaturization takes place by increasing integration onto a single semiconductor die, commonly known as an integrated circuit or as a chip. As is well known, some circuit functions are better performed by chips formed on one type of semiconductor process whereas other circuit functions are better performed by chips formed on a different type of semiconductor process. Examples of such disparate circuit functions include analog versus digital circuits, and also high power versus low power circuit applications. Generally, a single chip cannot be manufactured with two or more different semiconductor processes.
To miniaturize an electronic system having chips formed using different semiconductor fabrication technologies, a trend in the integrated circuit industry is to electrically couple such circuits together. Currently, the industry has techniques for positioning two die side by side, each die of a different fabrication technology. Each die is picked and placed into a package. There are bonding wires that connect each die to external connections and/or to each other. This is referred to as a side by side technique. Another technique for joining two disparate chips together is to stack a first die on top of a second die, usually both die are face up. Each of these two die are electrically coupled to external connections and/or interconnected via bond wires. This is referred to as a stacked die technique. A modification of the stacked die technique is that the first die is configured as a flip-chip die. To assemble the first die and the second die, the first die is flipped upside down, then picked and placed onto the top of the second die, such that the “top” surface, now upside down, of the first die is placed on the top surface of the second die. The interface surfaces of both the first die and the second die are configured with solder ball interconnects such that some level of interconnect is formed between the first die and the second die when assembled. This modified stacked die technique can be performed using a CSP (Chip Scale Package) type technology. In either the side by side technique or the stacked die technique, the first die is singulated meaning the wafer on which the first die was fabricated has been cut to form separate, individual die, the second die is singulated, and the assembly process requires some means to pick and place the two together and connect them. An advantage of the side by side technique and the stacked die technique is that all die can be pre-tested for proper functionality, and are therefore known good die.
Another technique for connecting disparate type die is a wafer bonding technique, which forms three-dimensional metal interconnects between die on the wafers being bonded. In some cases, such three-dimensional metal interconnects include through silicon vias. The wafer bonding technique bonds together a first wafer and a second wafer, where the second wafer has die of a different technology than the die on the first wafer, but the die on both wafers have the same size, spacing, and repetition rate. There are exposed metal interconnects on a surface of each die for both the first wafer and the second wafer. The two wafers are placed together so that the surfaces with exposed metal interconnects face each other. The two wafers are bonded together and the interconnects of the interfacing surfaces of the two wafers are intimately connected. This bonds one die, on the first wafer, on top of another die, on the second wafer. The bonded wafer stack is then cut to singulate the individual die stacks. The bonding of the two wafers is done according to the chemical compositions of the two wafers. There are other chemistries that can be used. For example, there can be other types of material(s) that are deposited on the wafers so that when the two wafers are bonded together, the melting temperature for those interface materials is used. Other bonding techniques can be used that are well known in the art.
One advantages of the wafer bonding technique is that a high density of interconnects can be achieved between the two wafers because the wafers typically have very fine geometry resolution interconnects and therefore the metalization between the two wafers is at a small level. In comparison to the stacked die technique that uses solder balls, where the solder balls are typically 100 microns or more in diameter, has a number of interconnects that is much more limited. As such, the parasitic characteristics associated with the interconnects are lower using the wafer bonding technique than the stacked die technique. Also, the stacked die technique uses a pick and place process, where each die is individually placed. In contrast, the wafer bonding technique uses a batch process, so there is economies of scale.
The wafer bonding technique has several disadvantages. First, the wafer bonding technique requires that each die on the first wafer is equal in size to each die on the second wafer. If the die are not the same size, the small die will require wasted space be formed between adjacent die to provide the same spacing as for the larger die on the other wafer. Second, the wafer bonding technique requires that the first wafer is equal in size to the second wafer. Third, the bonding of two wafers limits interfacing to two separate technologies, a first technology of the first wafer, such as CMOS formed of silicon technology, and a second technology of the second wafer, such as Galium Arsenide (GaAs) or Galium Nitride (GaN). However, the face-to-face interface of the first and second wafers does not enable a configuration to introduce a third, or more, additional technology. A fourth disadvantage of the wafer bonding technique is that the die on each wafer are not pre-tested for proper functionality, and are therefore subject to yield constraints for both the first wafer and the second wafer. In other words, there is a first defect density associated with the first wafer, and there is a second defect density associated with the second wafer. Stacking and bonding the two wafers means the resulting die stacks have defect densities that are cumulative of both the first wafer and the second wafer. A die stack with a first die from the first wafer and a second die from the second wafer may be defective if either the first die is defective or the second die is defective.
If the conditions for wafer bonding are not met, then it is possible to singulate the die of the first wafer and to attach the singulated first die to the second die still part of the second wafer using a pick and place technique. Pick and place machines are robotic machines used to place surface-mount devices onto a printed circuit board (PCB) or other substrate. This technique has the disadvantage that it is not done in batch mode. Another disadvantage is that applications requiring precise placement necessitate high resolution, high precision robotic equipment to properly align and place the singulated first die on the second die.
Fluidic self-assembly is a process by which die are added to a fluid solution, which is then distributed across a substrate. One type of fluidic self-assembly is a shaped-based technique. Cavities of a specified shape and size are formed in a top surface of the substrate. The shape and size of the die and the corresponding cavities are such that a die falls into a cavity according to a specific alignment, thereby self-aligning.
FIG. 1 illustrates a cut-out side view of a substrate 2 having a plurality of cavities 4 formed in a top surface 6 of the substrate 2. In an exemplary configuration, a cut-out side profile of each cavity is trapezoidal in shape. In the case of silicon, the trapezoidal shape is a result of a standard etching process that creates sidewalls with very precise angles. As shown in FIG. 1, each of the trapezoidal-shaped cavities has sides 8 that taper inward moving downward from the top surface 6. As is well known, the trapezoidal-shaped cavities can be formed using an appropriate etch process on a surface of a silicon wafer in a proper crystal orientation. The number and positions of the cavities are formed according to a specified pattern across the top surface of the substrate. The cavities are formed such that correspondingly shaped and sized die can be positioned within the cavities accordingly to a specific alignment. The die are fabricated from a second substrate using known semiconductor integrated circuit fabrication technology. Once singulated, the die have a shape and size complimentary to the cavities 4 in the substrate 2, for example the trapezoidal cross section shape and a size to correspond to the cavities 4. In some embodiments, the active circuitry of each die is on the elongated, or top surface, of the trapezoidal shape. The plurality of singulated die are placed in a fluid, typically water. The substrate 2 is positioned at an angle, such as shown in FIG. 2, and the fluid with die 10 is poured down the angled substrate 2 so that the die are gravity fed down the face of the angled substrate. Because the cavities 4 on the substrate 2 are trapezoidal-shaped, and the die 10 have the same trapezoidal shape, and because the cavities 4 have a predetermined size, and the die 10 have the corresponding size, there is only one orientation where a die 10 fits within a cavity 4, thereby self-assembling the die 10 within the substrate 2.
Referring to FIGS. 1 and 2, a die 10 can only fall into the cavity 4 with the bottom, narrower portion of the die positioned at the bottom of the cavity and the top, wider portion of the die positioned at the top of the cavity. In other words, the die is positioned narrow-side down in the cavity. Referring to FIG. 2, only the left hand die 10 is oriented properly to fit within one of the cavities 4. The other two die shown are not properly aligned and therefore will not properly fall within any of the cavities 4 while in their current alignment. During fluid flow, the die are constantly moving and therefore shifting their alignment. Any die 10 that do not fall into a cavity 4 on the substrate 2 are recirculated to flow back down the angled substrate 2. This cycling can be performed as many times as desired, until all the cavities 4 on the substrate 2 are filled with die 10, such as shown in FIG. 3. The cavities and die can be configured to properly align in the z-direction (top and bottom surfaces) and also in the x and y-directions such that each specific side of the die is aligned with a specific side of the cavity. In general, the die and the cavities are fabricated with geometries that allow the die to fit correctly and to be properly oriented within the cavity.
The die can be held in place within the cavities by pre-applying a surface treatment within the cavity prior to self-assembly, or by applying a securing means to the die after self-assembly, such as adhesive, solder, or a strap. Electrical connections can be made to the die assembled in the substrate. For example, bonding wires are added to electrically connect the die to metal interconnects on the substrate.